 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MCP6271/1R/2/3/4/5 170 A, 2 MHz Rail-to-Rail Op Amp Features * * * * * * * Gain Bandwidth Product: 2 MHz (typ.) Supply Current: IQ = 170 A (typ.) Supply Voltage: 2.0V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in Single, Dual and Quad Packages Parts with Chip Select (CS) - Single (MCP6273) - Dual (MCP6275) Description The Microchip Technology Inc. MCP6271/1R/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 2 MHz Gain Bandwidth Product (GBWP) and a 65 Phase Margin. This family also operates from a single supply voltage as low as 2.0V, while drawing 170 A (typ.) quiescent current. The MCP6271/1R/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. This family of op amps is designed with Microchip's advanced CMOS process. The MCP6275 has a Chip Select input (CS) for dual op amps in an 8-pin package and is manufactured by cascading two op amps (the output of op amp A connected to the non-inverting input of op amp B). The CS input puts the device in low power mode. The MCP6271/1R/2/3/4/5 family operates over the Extended Temperature Range of -40C to +125C, with a power supply range of 2.0V to 5.5V. Applications * * * * * * Automotive Portable Equipment Photodiode Amplifier Analog Filters Notebooks and PDAs Battery Powered Systems Available Tools * SPICE Macro Model (at www.microchip.com) * FilterLab(R) Software (at www.microchip.com) Package Types MCP6271 PDIP, SOIC, MSOP NC 1 VIN- 2 VIN+ 3 VSS 4 + 8 NC 7 VDD 6 VOUT 5 NC VOUT 1 VSS 2 VIN+ 3 4 VIN- + MCP6271 SOT-23-5 5 VDD MCP6271R SOT-23-5 VOUT 1 VDD 2 VIN+ 3 4 VIN- + 5 VSS VOUTA 1 VINA- 2 VINA+ 3 VSS 4 MCP6272 PDIP, SOIC, MSOP 8 VDD -+ +7 VOUTB 6 VINB- 5 VINB+ MCP6273 PDIP, SOIC, MSOP NC 1 VIN- 2 VIN+ 3 VSS 4 + 8 CS 7 VDD 5 NC VOUT 1 VSS 2 MCP6273 SOT-23-6 5 CS 6 VDD VOUTA 1 VINA- 2 VDD 4 VINB+ 5 VINB- 6 VOUTB 7 + 4 VIN- VINA+ 3 MCP6274 PDIP, SOIC, TSSOP - + + - 13 VIND- 12 VIND+ 11 VSS 10 VINC+ -+ +- 9 V - INC 8 VOUTC 14 VOUTD VOUTA/VINB+ 1 VINA- 2 VINA+ 3 VSS 4 MCP6275 PDIP, SOIC, MSOP 8 VDD -+ +- 7 VOUTB 6 VINB- 5 CS 6 VOUT VIN+ 3 (c) 2006 Microchip Technology Inc. DS21810E-page 1 MCP6271/1R/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.1.2 "Input Voltage and Current Limits". Absolute Maximum Ratings VDD - VSS ........................................................................7.0V Current at Analog Input Pins (VIN+ and VIN-) ...............2 mA Analog Inputs (VIN+ and VIN-) .. VSS - 1.0V to VDD + 1.0V All other Inputs and Outputs .......... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current .................................Continuous Current at Output and Supply Pins ............................30 mA Storage Temperature....................................-65C to +150C Junction Temperature (TJ) . .........................................+150C ESD Protection On All Pins (HBM/MM) ................ 4 kV/400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CS is tied low. Parameters Input Offset (Note 1) Input Offset Voltage Input Offset Voltage (Extended Temperature) Input Offset Temperature Drift Power Supply Rejection Ratio Input Bias Current and Impedance Input Bias Current At Temperature At Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode (Note 4) Common Mode Input Voltage Range Common Mode Rejection Ratio Common Mode Rejection Ratio Open-Loop Gain DC Open-Loop Gain (Large Signal) Note 1: 2: 3: 4: AOL 90 110 -- dB VOUT = 0.2V to VDD - 0.2V, VCM = VSS (Note 1) VCMR VCMR CMRR CMRR VSS - 0.15 VSS - 0.30 70 65 -- -- 85 80 VDD + 0.15 VDD + 0.30 -- -- V V dB dB VDD = 2.0V (Note 5) VDD = 5.5V (Note 5) VCM = -0.3V to 2.5V, VDD = 5V (Note 6) VCM = -0.3V to 5.3V, VDD = 5V (Note 6) IB IB IB IOS ZCM ZDIFF -- -- -- -- -- -- 1.0 50 2 1.0 10 ||6 1013||3 13 Sym VOS VOS VOS/TA PSRR Min -3.0 -5.0 -- 70 Typ -- -- 1.7 90 Max +3.0 +5.0 -- -- -- 200 5 -- -- -- Units mV mV VCM = VSS Conditions TA = -40C to +125C, VCM = VSS V/C TA = -40C to +125C, VCM = VSS dB pA pA nA pA VCM = VSS Note 2 TA= +85C (Note 2) TA= +125C (Note 2) Note 3 ||pF Note 3 ||pF Note 3 5: 6: The MCP6275's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6275's VINB- pin is specified by IB only. This specification does not apply to the MCP6275's VOUTA/VINB+ pin. The MCP6275's VINB- pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to VDD - 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. Set by design and characterization. Does not apply to op amp B of the MCP6275. DS21810E-page 2 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CS is tied low. Parameters Output Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: 3: 4: VDD IQ 2.0 100 -- 170 5.5 240 V A IO = 0 VOL, VOH ISC VSS + 15 -- -- 25 VDD - 15 -- mV mA 0.5V output overdrive (Note 4) Sym Min Typ Max Units Conditions 5: 6: The MCP6275's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6275's VINB- pin is specified by IB only. This specification does not apply to the MCP6275's VOUTA/VINB+ pin. The MCP6275's VINB- pin (op amp B) has a common mode input voltage range (VCMR) of VSS + 100 mV to VDD - 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. Set by design and characterization. Does not apply to op amp B of the MCP6275. AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF and and CS is tied low. Parameters AC Response Gain Bandwidth Product Phase Margin Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 4.6 20 3 -- -- -- VP-P nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz GBWP PM SR -- -- -- 2.0 65 0.9 -- -- -- MHz V/s G = +1 Sym Min Typ Max Units Conditions TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 6L-SOT-23 Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note: JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 256 230 85 163 206 70 120 100 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Note Sym Min Typ Max Units Conditions The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. (c) 2006 Microchip Technology Inc. DS21810E-page 3 MCP6271/1R/2/3/4/5 MCP6273/MCP6275 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF and and CS is tied low. Parameters CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High GND Current per Amplifier Amplifier Output Leakage Dynamic Specifications (Note 1) CS Low to Valid Amplifier Output, Turn on Time CS High to Amplifier Output High-Z Hysteresis Note 1: tON -- 4 10 s CS Low 0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 VDD/2, VDD = 5.0V CS High 0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 VDD/2 VDD = 5V VIH ICSH ISS -- 0.8VDD -- -- -- -- 0.7 -0.7 0.01 VDD 2 -- -- V A A A CS = VDD CS = VDD CS = VDD VIL ICSL VSS -- -- 0.01 0.2VDD -- V A CS = VSS Sym Min Typ Max Units Conditions tOFF VHYST -- -- 0.01 0.6 -- -- s V The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic specification is tested at the output of op amp B (VOUTB). CS VIL tON VIH tOFF High-Z -0.7 A (typ.) -170 A (typ.) 0.7 A (typ.) 10 nA (typ.) VOUT High-Z -0.7 A (typ.) ISS 0.7 A (typ.) ICS FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. DS21810E-page 4 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF and CS is tied low. 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 0.0 0.6 1.2 1.8 2.4 -3.0 -2.4 -1.8 -1.2 -0.6 3.0 Input Offset Voltage (mV) 14% Percentage of Occurrences 12% 10% 8% 6% 4% 2% 0% -8 -6 -4 -2 0 2 4 6 -10 8 2.8 5.5 Input Offset Voltage Drift (V/C) 10 6.0 3.0 Percentage of Occurrences 832 Samples VCM = VSS 832 Samples VCM = VSS TA = -40C to +125C FIGURE 2-1: 32% Percentage of Occurrences 28% 24% 20% 16% 12% 8% 4% 0% 0 10 20 Input Offset Voltage. FIGURE 2-4: 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Input Offset Voltage Drift. Percentage of Occurrences 422 Samples TA = 85C 422 Samples TA = +125C 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 4.5 30 40 50 60 70 80 Input Bias Current (pA) 90 100 Input Bias Current (nA) FIGURE 2-2: TA = +85C. 300 Input Offset Voltage (V) 250 200 150 100 50 0 -50 -100 -0.4 -0.2 0.0 0.2 VDD = 2.0V Input Bias Current at FIGURE 2-5: TA = +125C. 300 Input Offset Voltage (V) 250 200 150 100 50 0 -50 -100 -0.5 0.0 0.5 1.0 VDD = 5.5V Input Bias Current at TA = +125C TA = +85C TA = +25C TA = -40C 1.5 2.0 2.5 3.0 3.5 4.0 5.0 TA = +125C TA = +85C TA = +25C TA = -40C 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V. (c) 2006 Microchip Technology Inc. DS21810E-page 5 2.6 MCP6271/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (Continued) Note: Unless otherwise indicated, TA = +25C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF, and CS is tied low. 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 Common Mode Input Voltage Range Limit (V) Typical lower (VCM - VSS) limit Common Mode Input Voltage Range Limit (V) VDD = 5.5V VDD = 2.0V VDD = 2.0V Typical upper (VCM - VDD) limit -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 VDD = 5.5V -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature. 300 Input Offset Voltage (V) 250 200 150 100 50 0 -50 -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) VDD = 2.0V VDD = 5.5V FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature. 10,000 Input Bias, Offset Currents (pA) 1,000 100 10 1 45 55 65 75 85 95 105 115 125 Ambient Temperature (C) VCM = VSS Representative Part VCM = VDD VDD = 5.5V Input Bias Current Input Offset Current FIGURE 2-8: Output Voltage. 110 100 CMRR, PSRR (dB) 90 80 70 60 50 40 30 Input Offset Voltage vs. FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature. 120 CMRR PSRR, CMRR (dB) 110 100 90 80 70 60 -50 -25 0 25 50 75 100 125 Ambient Temperature (C) PSRR (VCM = VSS) CMRR PSRR- PSRR+ 20 1 10 100 1k 10k 100k 1M 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Frequency (Hz) FIGURE 2-9: Frequency. CMRR, PSRR vs. FIGURE 2-12: Temperature. CMRR, PSRR vs. DS21810E-page 6 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (Continued) Note: Unless otherwise indicated, TA = +25C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF, and CS is tied low. 55 Input Bias, Offset Currents (pA) Input Bias, Offset Currents (nA) 45 35 25 15 5 -5 -15 -25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) TA = 85C VDD = 5.5V Input Offset Current Input Bias Current 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) TA = 125C VDD = 5.5V Input Offset Current Input Bias Current FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85C. 250 Quiescent Current (A/amplifier) 200 150 100 50 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) TA = +125C TA = +85C TA = +25C TA = -40C FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125C. 1000 Ouput Voltage Headroom (mV) 100 10 VOL - VSS VDD - VOH 1 0.01 0.1 1 Output Current Magnitude (mA) 10 FIGURE 2-14: Supply Voltage. 120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20 1.E+00 1.E+01 1.E+02 Phase Quiescent Current vs. FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. 3.0 Gain Bandwidth Product (MHz) Open-Loop Phase () 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 0 25 50 75 100 Ambient Temperature (C) PM, VDD = 5.5V VDD = 2.0V GBWP, VDD = 5.5V VDD = 2.0V 80 75 70 65 60 55 50 125 Phase Margin () 0 -30 Gain -60 -90 -120 -150 -180 -210 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 0.1 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) 1.E+08 1.E-01 FIGURE 2-15: Frequency. Open-Loop Gain, Phase vs. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature. (c) 2006 Microchip Technology Inc. DS21810E-page 7 MCP6271/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (Continued) Note: Unless otherwise indicated, TA = +25C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF, and CS is tied low. 10 Maximum Output Voltage Swing (V P-P ) VDD = 5.5V VDD = 2.0V 1.8 1.6 Slew Rate (V/s) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.E+03 1.E+04 1.E+05 1.E+06 1k 10k 100k Frequency (Hz) 1M 10M 1.E+07 0.0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125 Rising Edge VDD = 2.0V Falling Edge VDD = 5.5V 1 0.1 FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency. 1,000 Input Noise Voltage Density (nV/ Hz) FIGURE 2-22: Slew Rate vs. Temperature. 25 Input Noise Voltage Density (nV/ Hz) 20 15 10 5 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Input Voltage (V) 5.5 100 100 f = 1 kHz VDD = 5.0V 10 0.1 1 10 100 1k 10k 100k 1M 1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 01 00 01 Frequency (Hz) 04 02 03 05 06 FIGURE 2-20: vs. Frequency. 35 Ouptut Short-Circuit Current (mA) Input Noise Voltage Density FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz. 140 Channel-to-Channel Separation (dB) 130 120 110 100 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) TA = +125C TA = +85C TA = +25C TA = -40C 1 10 Frequency (kHz) FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274). DS21810E-page 8 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (Continued) Note: Unless otherwise indicated, TA = +25C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF, and CS is tied low. 250 VDD = 2.0V Quiescent Current (A/amplifier) 200 150 100 50 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Chip Select Voltage (V) CS swept High-to-Low Hysteresis CS swept Low-to-High Op Amp turns On Op Amp turns Off Quiescent Current (A/amplifier) 700 600 500 400 300 200 100 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) CS swept High-to-Low VDD = 5.5V Hysteresis CS swept Low-to-High Op Amp turns On/Off FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only). 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Time (5 s/div) G = +1 V/V VDD = 5.0V FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). 5.0 4.5 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Time (5 s/div) G = -1 V/V VDD = 5.0V FIGURE 2-26: Pulse Response. Large Signal Non-inverting FIGURE 2-29: Response. Large Signal Inverting Pulse G = +1 V/V Output Voltage (10 mV/div) Output Voltage (10 mV/div) G = -1 V/V Time (2 s/div) Time (2 s/div) FIGURE 2-27: Pulse Response. Small Signal Non-inverting FIGURE 2-30: Response. Small Signal Inverting Pulse (c) 2006 Microchip Technology Inc. DS21810E-page 9 MCP6271/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (Continued) Note: Unless otherwise indicated, TA = +25C, VCM = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, CL = 60 pF, and CS is tied low. 2.5 Chip Select, Output Voltages (V) 2.0 1.5 1.0 0.5 0.0 Time (5 s/div) VOUT CS Chip Select, Output Voltages (V) VDD = 2.0V G = +1 V/V VIN = VSS Output On Output High-Z 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 CS VDD = 5.5V G = +1 V/V VIN = VSS VOUT Output High-Z Time (5 s/div) Output On FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only). 1.E-02 10m 1.E-03 1m 1.E-04 100 1.E-05 10 1.E-06 1 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only). 6 Input, Output Voltage (V) 5 4 3 2 1 0 -1 Time (1 ms/div) VIN VOUT Input Current Magnitude (A) VDD = 5.0V G = +2 V/V +125C +85C +25C -40C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-32: Voltage. Input Current vs. Input FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal. DS21810E-page 10 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6271 (SOT-23-5) 4 3 2 1 5 -- -- MCP6271R (SOT-23-5) 4 3 5 1 2 -- -- MCP6273 (PDIP, SOIC, MSOP) 2 3 4 6 7 8 1,5 MCP6273 (SOT-23-6) 4 3 2 1 6 5 -- Symbol VIN- VIN+ VSS VOUT VDD CS NC Description Inverting Input Non-inverting Input Negative Power Supply Analog Output Positive Power Supply Chip Select No Internal Connection MCP6271 (PDIP, SOIC, MSOP) 2 3 4 6 7 -- 1,5,8 TABLE 3-2: MCP6272 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- -- PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6274 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- -- MCP6275 -- 2 3 8 -- 6 7 -- -- -- 4 -- -- -- 1 5 Symbol VOUTA VINA- VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD VOUTA / VINB+ CS Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) Analog Output (op amp A)/Non-inverting Input (op amp B) Chip Select Description 3.1 Analog Outputs 3.4 CS Digital Input The output pins are low impedance voltage sources. This is a CMOS, Schmitt triggered input that places the part into a low power mode of operation. 3.2 Analog Inputs The non-inverting and inverting inputs are high impedance CMOS inputs with low bias currents. 3.5 Power Supply (VSS and VDD) 3.3 MCP6275's VOUTA/VINB+ Pin The positive power supply (VDD) is 2.0V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 F to 0.1 F) within 2 mm of the VDD pin. These parts need to use a bulk capacitor (within 100 mm), which can be shared with nearby analog parts. For the MCP6275 only, the output of op amp A is connected directly to the non-inverting input of op amp B; this is the VOUTA/VINB+ pin. This connection makes it possible to provide a CS pin for duals in 8-pin packages. (c) 2006 Microchip Technology Inc. DS21810E-page 11 MCP6271/1R/2/3/4/5 4.0 APPLICATION INFORMATION The MCP6271/1R/2/3/4/5 family of op amps is manufactured using Microchip's state of the art CMOS process, specifically designed for low cost, low power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth make the MCP6271/1R/2/3/4/5 ideal for battery powered applications. In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Absolute Maximum Ratings at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 R1 V2 R2 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > D2 MCP627X VOUT 4.1 Rail-to-Rail Inputs The input stage of the MCP6271/1R/2/3/4/5 op amps uses two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM, which is aproximately equal to VIN+ and VIN- in normal operation) and the other at high VCM. With this topology, the input operates with VCM up to 0.3V past either supply rail (see Figure 2-7 and Figure 2-10). The input offset voltage (VOS) is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. The transition between the two input stage occurs when VCM VDD - 1.1V (see Figure 2-3 and Figure 26). For the best distortion and gain linearity, with noninverting gains, avoid this region of operation. 4.1.1 PHASE REVERSAL The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-34 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS FIGURE 4-2: Inputs. Protecting the Analog The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-32. Applications that are high impedance may need to limit the useable voltage range. 4.2 Rail-to-Rail Output VIN+ Bond Pad Input Stage Bond V - IN Pad The output voltage range of the MCP6271/1R/2/3/4/5 op amps is VDD - 15 mV (min.) and VSS + 15 mV (max.) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-17 for more information. VSS Bond Pad FIGURE 4-1: Structures. Simplified Analog Input ESD DS21810E-page 12 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 4.3 Capacitive Loads 4.4 MCP6273/5 Chip Select (CS) Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. The MCP6273 and MCP6275 are single and dual op amps with Chip Select (CS), respectively. When CS is pulled high, the supply current drops to 0.7 A (typ.) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high impedance state. By pulling CS low, the amplifier is enabled. The CS pin has a 5 M (typ.) pull-down resistor connected to VSS, so it will go low if the CS pin is left floating. Figure 1-1 shows the output voltage and supply current response to a CS pulse. 4.5 Cascaded Dual Op Amps (MCP6275) - VIN MCP627X + RISO VOUT CL The MCP6275 is a dual op amp with Chip Select (CS). The Chip Select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This pin is available because the output of op amp A connects to the non-inverting input of op amp B, as shown in Figure 4-5. The Chip Select input, which can be connected to a microcontroller I/O line, puts the device in low power mode. Refer to Section 4.4 "MCP6273/5 Chip Select (CS)". VOUTA/VINB+ 1 VINA- VINA+ 2 3 A MCP6275 5 CS B VINB- 6 7 VOUTB FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 1,000 Recommended RISO ( ) FIGURE 4-5: Cascaded Gain Amplifier. 100 GN = 1 V/V GN = 2 V/V GN 4 V/V 10 10 100 1,000 10,000 Normalized Load Capacitance; CL / GN (pF) The output of op amp A is loaded by the input impedance of op amp B, which is typically 10136 pF, as specified in the DC specification table (Refer to Section 4.3 "Capacitive Loads" for further details regarding capacitive loads). The common mode input range of these op amps is specified in the data sheet as VSS - 300 mV and VDD + 300 mV. However, since the output of op amp A is limited to VOL and VOH (20 mV from the rails with a 10 k load), the non-inverting input range of op amp B is limited to the common mode input range of VSS + 20 mV and VDD - 20 mV. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6271/1R/2/3/4/5 SPICE macro model are helpful. (c) 2006 Microchip Technology Inc. DS21810E-page 13 MCP6271/1R/2/3/4/5 4.6 Unused Amplifiers An unused op amp in a quad package (MCP6274) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. In Circuit A, R1 and R2 produce a voltage within its output voltage range (VOH, VOL). The op amp buffers this voltage, which can be used elsewhere in the circuit. Circuit B uses the minimum number of components and operates as a comparator. 1/4 MCP6274 (A) VDD R1 R2 VDD 1/4 MCP6274 (B) VDD VIN- VIN+ VSS Guard Ring FIGURE 4-7: for Inverting Gain. 1. Example Guard Ring Layout FIGURE 4-6: Unused Op Amps. 2. 4.7 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good, high frequency performance. It also needs a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. For Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. 4.8 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow. This is greater than the MCP6271/1R/2/3/4/5 family's bias current at 25C (1 pA, typ.). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is illustrated in Figure 4-7. DS21810E-page 14 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 4.9 4.9.1 Application Circuits ACTIVE FULL-WAVE RECTIFIER 4.9.2 LOSSY NON-INVERTING INTEGRATOR The MCP6271/1R/2/3/4/5 family of amplifiers can be used in applications such as an Active Full-Wave Rectifier or an Absolute Value circuit, as shown in Figure 4-8. The amplifier and feedback loops in this active voltage rectifier circuit eliminate the diode drop problem that exists in a passive voltage rectifier. This circuit behaves as a follower (the output follows the input) as long as the input signal is more positive than the reference voltage. If the input signal is more negative than the reference voltage, however, the circuit behaves as an inverting amplifier. Therefore, the output voltage will always be above the reference voltage, regardless of the input signal. R2 VIN R1 - R3 R4 R5 Op Amp B VOUT + 1/2 MCP6272 VREF D2 D1 The non-inverting integrator shown in Figure 4-9 is easy to build. It saves one op amp over the typical Miller integrator plus inverting amplifier configuration. The phase accuracy of this integrator depends on the matching of the input and feedback resistor-capacitor time constants. RF makes this a lossy integrator (it has finite gain at DC), and makes this integrator stable by itself. R1 + C1 MCP6271 _ RF C2 R2 VOUT VIN RF R2 R 1 C 1 = ( R 2 ||R F )C 2 V OUT 1------------- ------------------- , V IN s ( R1 C1 ) 1 f -------------------------------------------------2R 1 C 1 ( 1 + R F R 2 ) FIGURE 4-9: R1 = R2 = R3 Non-Inverting Integrator. - Op Amp A + 1/2 MCP6272 Input VREF V D1 R 4 < R 3 1 - --------------------------- V REF - V SS R2 R4 R 5 = -----------2R 3 Output VREF VREF time time FIGURE 4-8: Active Full-wave Rectifier. The design equations give a gain of 1 from VIN to VOUT, and produce rail-to-rail outputs. (c) 2006 Microchip Technology Inc. DS21810E-page 15 MCP6271/1R/2/3/4/5 4.9.3 CASCADED OP AMP APPLICATIONS R4 R3 R2 R1 The MCP6275 provides the flexibility of Low power mode for dual op amps in an 8-pin package. The MCP6275 eliminates the added cost and space in a battery powered application by using two single op amps with Chip Select (CS) lines or a 10-pin device with one CS line for both op amps. Since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with a CS line becomes suitable. The circuits below show possible applications for this device. B VIN A MCP6275 VOUT CS FIGURE 4-11: Configuration. 4.9.3.3 Cascaded Gain Circuit 4.9.3.1 Load Isolation Difference Amplifier With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistive loads in the feedback loop (such as an integrator or filter circuit) the op amp may not have sufficient source current to drive the load. In this case, op amp B can be used as a buffer. Figure 4-12 shows op amp A configured as a difference amplifier with Chip Select. In this configuration, it is recommended that well matched resistors (e.g., 0.1%) be used to increase the Common Mode Rejection Ratio (CMRR). Op amp B can be used to provide additional gain and isolate the load from the difference amplifier. R2 R1 R4 R3 VIN2 B A MCP6275 Load VOUTB VIN1 R2 R1 B A MCP6275 VOUT CS CS FIGURE 4-10: Buffer. 4.9.3.2 Isolating the Load with a FIGURE 4-12: 4.9.3.4 Difference Amplifier Circuit. Cascaded Gain Inverting Integrator with Active Compensation and Chip Select Figure 4-11 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A and B, as shown below: V OUT = V IN G A G B + V OSA G A G B + V OSB G B Where: GA GB VOSA VOSB = = = = op amp A gain op amp B gain op amp A input offset voltage op amp B input offset voltage Figure 4-13 uses an active compensator (op amp B) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. This circuit uses op amp B as a unity gain buffer to isolate the integration capacitor C1 from op amp A and drives the capacitor with a low impedance source. Since both op amps are matched very well, they provide a high quality integrator. R1 C1 B A MCP6275 VOUT VIN Therefore, it is recommended that you set most of the gain with op amp A and use op amp B with relatively small gain (e.g., a unity gain buffer). CS FIGURE 4-13: Compensation. Integrator Circuit with Active DS21810E-page 16 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 4.9.3.5 Second Order MFB with an Extra Pole-Zero Pair 4.9.3.7 Capacitorless Second Order Low-Pass filter with Chip Select Figure 4-14 is a second order multiple feedback lowpass filter with Chip Select. Use the FilterLab(R) software from Microchip Technology Inc. to determine the R and C values for op amp A's second order filter. Op amp B can be used to add a pole-zero pair using C3, R6 and R7. R6 R1 VIN R3 R2 R5 R4 CS C1 C3 R7 B VOUT The low-pass filter shown in Figure 4-16 does not require external capacitors and uses only three external resistors; the op amp's GBWP sets the corner frequency. R1 and R2 are used to set the circuit gain. R3 is used to set the Q. To avoid gain peaking in the frequency response, Q needs to be low (lower values need to be selected for R3). Note that the amplifier bandwidth varies greatly over temperature and process. This configuration, however, provides a low cost solution for applications with high bandwidth requirements. R2 R3 MCP6275 VREF MCP6275 A B VOUT R1 VIN A VDD FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra PoleZero Pair. 4.9.3.6 Second Order Sallen-Key with an Extra Pole-Zero Pair CS FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select. Figure 4-15 is a second order Sallen-Key low-pass filter with Chip Select. Use the Filterlab(R) software from Microchip to determine the R and C values for op amp A's second order filter. Op amp B can be used to add a pole-zero pair using C3, R5 and R6. R5 R2 VIN R4 R3 C2 R1 C3 R6 B A MCP6275 C1 CS VOUT FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. (c) 2006 Microchip Technology Inc. DS21810E-page 17 MCP6271/1R/2/3/4/5 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6271/1R/2/3/4/5 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6271/1R/2/3/4/5 op amps is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation at room temperature. See the macro model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab(R) Software Microchip's FilterLab software is an innovative tool that simplifies analog active filter (using op amps) design. It is available free of charge from our web site at www.microchip.com. The FilterLab software tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21810E-page 18 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SOT-23 (MCP6271 and MCP6271R) Example: Device Code CGNN ETNN XXNN MCP6271 MCP6271R CG25 Example: Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP6273) XXNN 8-Lead MSOP XXXXXX YWWNNN CK25 Example: 6271E 644256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW MCP6271 E/P256 0437 Example: MCP6271 e3 E/P^^256 0644 OR 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN MCP6271 E/SN0437 256 Example: MCP6271E e3 SN^^0644 256 OR Legend: XX...X Y YY WW NNN * Note: e3 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2006 Microchip Technology Inc. DS21810E-page 19 MCP6271/1R/2/3/4/5 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6274) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP6274-E/P 0437256 OR MCP6274 e3 E/P^^ 0644256 14-Lead SOIC (150 mil) (MCP6274) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6274ESL 0437256 OR MCP6274 e3 E/SL^^ 0644256 14-Lead TSSOP (MCP6274) Example: XXXXXX YYWW NNN 6274EST 0437 256 DS21810E-page 20 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p B p1 D n 1 c A A2 Units Dimension Limits Number of Pins Pitch Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L f c B a b L A1 INCHES* MIN NOM 5 .038 .075 .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 .006 .017 5 5 .046 .043 .003 .110 .064 .116 .018 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0.90 0.90 0.00 2.60 1.50 2.80 0.35 MAX MIN MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 0 0.09 0 0 0.15 0.43 5 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Revised 09-12-05 Drawing No. C04-091 (c) 2006 Microchip Technology Inc. DS21810E-page 21 MCP6271/1R/2/3/4/5 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 B p1 D n 1 c A A2 L A1 Units Dimension Limits Number of Pins Pitch Outside lead pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L c B .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 MIN INCHES* NOM 6 .038 BSC .075 BSC .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0 0 0.90 0.90 0.00 2.60 1.50 2.80 0.35 0 0.09 MAX MIN MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 1.18 1.10 0.08 2.80 1.63 2.95 0.45 5 0.15 0.43 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 Revised 09-12-05 DS21810E-page 22 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 c A A1 Units Dimension Limits N e A Thickness A2 A1 E Width E1 D L L1 c b L1 MILLIMETERS NOM 8 0.65 BSC -- 0.85 -- 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.95 REF -- -- -- L MIN MAX Number of Pins Pitch Overall Height Molded Package Standoff Overall Width Molded Package Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead Width -- 0.75 0.00 1.10 0.95 0.15 0.40 0 0.08 0.22 0.80 8 0.23 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-111, Sept. 8, 2006 (c) 2006 Microchip Technology Inc. DS21810E-page 23 MCP6271/1R/2/3/4/5 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A A2 c L A1 eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21810E-page 24 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 (c) 2006 Microchip Technology Inc. DS21810E-page 25 MCP6271/1R/2/3/4/5 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A A2 c eB A1 B1 B p L Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21810E-page 26 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h 45 c A A2 L A1 MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .150 .157 3.99 Overall Length D .337 .347 8.81 Chamfer Distance h .010 .020 0.51 Foot Length L .016 .050 1.27 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .014 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 Revised 7-20-06 Units Dimension Limits n p MIN INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX MIN MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 (c) 2006 Microchip Technology Inc. DS21810E-page 27 MCP6271/1R/2/3/4/5 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 n B 1 A c L Units Dimension Limits MIN n p A A2 A1 E E1 D L c B .039 .033 .002 .246 .169 .193 .020 0 .004 .007 INCHES NOM 14 .026 BSC .041 .035 .004 .251 .173 .197 .024 4 .006 .010 12 REF 12 REF A1 MILLIMETERS* MAX MIN NOM 14 0.65 BSC .043 .037 .006 .256 .177 .201 .028 8 .008 .012 1.00 0.85 0.05 6.25 4.30 4.90 0.50 0 0.09 0.19 1.05 0.90 0.10 6.38 4.40 5.00 0.60 4 0.15 0.25 12 REF 12 REF A2 MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom 1.10 0.95 0.15 6.50 4.50 5.10 0.70 8 0.20 0.30 * Controlling Parameter Notes: Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tole rance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087 Revised: 08-17-05 DS21810E-page 28 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 APPENDIX A: REVISION HISTORY Revision E (December 2006) The following is the list of modifications: 1. Updated specifications (Section 1.0 "Electrical Characteristics"): a) Clarified Absolute Maximum Analog Input Voltage and Current specifications. b) Clarified VCMR, VOL, VOH, and PM specifications. c) Corrected the typical Eni. Added plots on Common Mode Input Range behavior vs. temperature and supply voltage (Section 2.0 "Typical Performance Curves"). Added applications writeup on unused op amps and corrected description of floating CS pin behavior (Section 4.0 "Application Information"). Updated package information (Section 6.0 "Packaging Information"): a) Corrected package markings. b) Added disclaimer to package outline drawings. 2. 3. 4. Revision D (December 2004) The following is the list of modifications: 1. 2. 3. 4. 5. Added SOT-23-5 packages for the DSTEMP and MCP6271R single op amps. Added SOT-23-6 packages for the DSTEMP single op amp. Added Section 3.0 "Pin Descriptions". Corrected application circuits (Section 4.9 "Application Circuits"). Added SOT-23-5 and SOT-23-6 packages and corrected package marking information (Section 6.0 "Packaging Information"). Added Appendix A: Revision History. 6. Revision C (June 2004) Revision B (October 2003) Revision A (June 2003) * Original data sheet release. (c) 2006 Microchip Technology Inc. DS21810E-page 29 MCP6271/1R/2/3/4/5 NOTES: DS21810E-page 30 (c) 2006 Microchip Technology Inc. MCP6271/1R/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - X /XX Package Examples: a) b) c) MCP6271-E/SN: MCP6271-E/MS: MCP6271-E/P: MCP6271T-E/OT: Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 5LD SOT-23 package. Temperature Range Device: MCP6271: MCP6271T: MCP6271RT: MCP6272: MCP6272T: MCP6273: MCP6273T: MCP6274: MCP6274T: MCP6275: MCP6275T: Single Op Amp Single Op Amp (Tape and Reel) (SOIC, MSOP, SOT-23-5) Single Op Amp (Tape and Reel) (SOT-23-5) Dual Op Amp Dual Op Amp (Tape and Reel) (SOIC, MSOP) Single Op Amp with Chip Select Single Op Amp with Chip Select (Tape and Reel) (SOIC, MSOP, SOT-23-6) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC, TSSOP) Dual Op Amp with Chip Select Dual Op Amp with Chip Select (Tape and Reel) (SOIC, MSOP) d) a) MCP6271RT-E/OT: Tape and Reel, Extended Temperature, 5LD SOT-23 package. MCP6272-E/SN: MCP6272-E/MS: MCP6272-E/P: MCP6272T-E/SN: Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 8LD SOIC package. a) b) c) d) a) Temperature Range: Package: E = -40C to +125C b) c) d) a) b) c) d) MCP6273-E/SN: OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6271, MCP6271R) CH = Plastic Small Outline Transistor (SOT-23), 6-lead (MCP6273) MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC, (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4 mm Body), 14-lead Extended Temperature, 8LD SOIC package. MCP6273-E/MS: Extended Temperature, 8LD MSOP package. MCP6273-E/P: Extended Temperature, 8LD PDIP package. MCP6273T-E/CH: Extended Temperature, 6LD SOT-23 package. MCP6274-E/P: MCP6274T-E/SL: MCP6274-E/SL: MCP6274-E/ST: Extended Temperature, 14LD PDIP package. Tape and Reel, Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package. Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 8LD SOIC package. a) b) c) d) MCP6275-E/SN: MCP6275-E/MS: MCP6275-E/P: MCP6275T-E/SN: (c) 2006 Microchip Technology Inc. DS21810E-page 31 MCP6271/1R/2/3/4/5 NOTES: DS21810E-page 32 (c) 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2006 Microchip Technology Inc. DS21810E-page 33 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 12/08/06 DS21810E-page 34 (c) 2006 Microchip Technology Inc. |
Price & Availability of MCP6275T-EST
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |